In recent years, there has been a dramatic increase in the internetworking of control units, sensor systems and actuatorics via a communications system and a communications link, for example in the form of a bus system, in the manufacturing of modern motor vehicles or also in machine manufacturing, especially in the machine tool sector, as well as in automation processes. Synergistic effects can be achieved in this context when functions are distributed among a plurality of control units. One speaks in this case of distributed systems.
To an increasing degree, communication among various participants in such a data transmission system is carried out via a bus system. The communications traffic on the bus system, access and receiving mechanisms, and error handling are governed by a protocol. A known protocol is the FlexRay protocol, for example; presently, it being based on the FlexRay protocol specification v2.1. FlexRay is a rapid, deterministic and fault-tolerant bus system which is especially conceived for use in motor vehicles. The FlexRay protocol functions in accordance with the time division multiple access (TDMA) principle, the participants, respectively the messages to be transmitted, having fixed time slots allocated thereto, during which they have exclusive access to the communications link. The time slots are repeated in a fixed cycle, making it possible to precisely predict the point in time when a message is transmitted over the bus, and for the bus access to be executed deterministically.
To enable optimal utilization of the bandwidth for transmitting messages on the bus system, FlexRay subdivides the cycle into a static and a dynamic segment. The fixed time slots are located in the static segment at the beginning of a bus cycle. In the dynamic segment, the time slots are dynamically predefined. In this segment, each exclusive bus access is permitted for only a brief time period, at least for the duration of what is commonly referred to as a minislot. Only when a bus access takes place within a minislot is the time slot extended by the requisite time period. Thus, bandwidth is only used when it is also actually needed. In this context, FlexRay communicates over two physically separate lines, each having a maximum data rate of 10 Mbit/s. However, FlexRay can also be operated at lower data rates. The two channels correspond to the physical layer, in particular of what is commonly referred to as the OSI (open systems interconnection) layer model. They are used primarily for the redundant and thus fault-tolerant transmission of messages, but are also capable of transmitting different types of messages, which would thereby double the data rate. It is also conceivable that the signal transmitted over the connection lines is derived from the difference between the signals transmitted via the two lines. The physical layer is designed to render possible either an electrical or an optical transmission of the signal(s) via the line(s) or a transmission via different paths.
To implement synchronous functions and to optimize data throughput by employing small intervals between two messages, the participants in the communications network require a common time base, what is commonly known as global time. For the clock synchronization, synchronization messages are transmitted in the static segment of the cycle, a special algorithm being used to correct the local clock time of the participants in accordance with the FlexRay specification in such a way that all local clocks run synchronously to a virtual global clock.
Processors, which are referred to as participant or host processors, are assigned to the participants of the data transmission system. A computer program, which makes it possible for the participant to perform a functionality assigned to it, for example a control and/or regulation function, is executed on these processors. To perform its functionality, the host processor can further process data received via the network structure from other participants in the data transmission system, for example from sensors. In the same way, the host processor can initiate a transmission of data that it generates in the course of performing its functionality, for example control data for actuators, via the network structure of the data transmission system to other participants of the data transmission system.
An operating system, which coordinates and controls the sequences of various processes and tasks of the computer system in order to implement the functionality of the participant, is run on the host processors. Under the related art, the known host processors typically have their own internal or external clock-pulse generator, which is designed as a quartz oscillator, for example, and which provides a clock signal for the host processor. The clock signal is independent of other external clock signals, which are utilized to synchronize the data transmission system to the global time base, for example. The operating system and the computer program running on the host processor, respectively the processes and tasks of the computer program, are synchronized to the clock signal of the internal or external clock-pulse generator.
Both the internal as well as the external clock-pulse generator of the host processor are discrete clock-pulse signals having a separate time base that is independent of the global time base to which all components of the data transmission system are synchronized. Thus, this means that the host processors of the participants in a data transmission system operate asynchronously, both from one another as well as from the data transmission system. For this reason, to transfer data between a data transmission system and a host processor, memory elements are typically provided into which data are written, which have either been received via the data transmission system for further processing by the host processor or which have been provided by the host processor for transmission via the data transmission system. If needed, the data stored in the memory element are then retrieved therefrom by the host processor for further processing, respectively by a communications controller of the data transmission system for transmission over the network structure. Since the data are stored in the memory elements and retrieved therefrom on the basis of different pulse durations, relatively long latency times can occur due to the lack of synchronization between the data transmission system and the host processor. Moreover, the timeliness of the data transmission, as well as the simultaneity or quasi-simultaneity of storing the data in the memory element and of retrieving the data therefrom are in no way ensured.
The time delays inherent in the transfer of data between the host processor and the data transmission system are particularly disadvantageous for an event-controlled data transmission since, in this case, the data transmission and the subsequent processing of the transmitted data in the host processor take place in response to a specific event and are typically supposed to trigger a specific function in response to this event within a specified time period. Due to the lack of synchronization between the host processor and the data transmission system, the situation can arise where the triggering of the function of the participant in response to the event is delayed or is even too late.
It is also conventional, prior to each data transfer between the data transmission system and the host processor of a participant, to preferably synchronize the operating-system time base in each instance to the global time base of the data transmission system by implementing the following steps:    a) querying between the host processor and the communications controller to determine the current bus clock rate of the data transmission system;    b) ascertaining the deviation from the operating-system time base and the requisite correction values; and    c) correcting the time base.
Considerable time and computational outlay are entailed in synchronizing the operating-system time base prior to each data transfer. In particular, steps a) and b) mentioned above necessitate considerable time and computational outlay for the synchronization processes.
German Published Patent Application No. 103 40 165 describes a method and a device for connecting sensors or actuators to a bus system. It is provided in this context for at least one of a plurality of phases of a signal processing in the sensor, respectively the actuator, to be synchronized to the time interval of the bus system. In particular, it is provided that the sensor or actuator be synchronized to a global time base of the bus system. The sensors and actuators known from this publication have a logic circuit via which they are able to participate in the bus traffic. Moreover, the known sensors and actuators have means for processing sensor signals in different clock pulse frequencies. However, the sensors and actuators do not have a processor having an operating system running thereon for implementing the functionality intended therefor. The sensors and actuators are the simplest and most primitive form of participants in a data transmission system which are able to be connected in a relatively simple manner to the data transmission system and synchronized to the global time base.
In the case of more complex participants, which have a host processor, for example, on which an operating system, preferably one having multitasking capability, runs, it is substantially more costly and complicated to connect the host processor to the data transmission system and to synchronize the operating-system time base and the global time base of the data transmission system.